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Updated Implementing post scarcity hardware (markdown)

Simon Brooke 2017-09-22 09:17:57 +01:00
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Implementing-post-scarcity-hardware.md

@ -29,7 +29,7 @@ There are other interesting chips which aren't strictly 64 core:
1. [Cavium ThunderX](https://www.servethehome.com/exclusive-first-cavium-thunderx-dual-48-core-96-core-total-arm-benchmarks)/ - ARM; 96 cores, each 64 bit, in pairs of two, shipping now; 1. [Cavium ThunderX](https://www.servethehome.com/exclusive-first-cavium-thunderx-dual-48-core-96-core-total-arm-benchmarks)/ - ARM; 96 cores, each 64 bit, in pairs of two, shipping now;
2. [Sparc M8](https://www.servethehome.com/oracle-sparc-m8-released-32-cores-256-threads-5-0ghz/) - 32 of 64 bit cores each capable of 8 concurrent threads; shipping now; 2. [Sparc M8](https://www.servethehome.com/oracle-sparc-m8-released-32-cores-256-threads-5-0ghz/) - 32 of 64 bit cores each capable of 8 concurrent threads; shipping now;
3. [Parallela Epiphany](https://www.parallella.org/board/) is a family of processors designed for parallel computation, with a 64 core unit shipping now and a 1024 core unit in prototype. Development boards are cheap. The processor architecture is RISC, but not ARM. 3. [Parallela Epiphany](https://www.parallella.org/board/) is a family of processors designed for parallel computation, with a 64 core unit shipping now and a [1024 core unit](https://www.parallella.org/2016/10/05/epiphany-v-a-1024-core-64-bit-risc-processor/) in prototype. Development boards are cheap. The processor architecture is RISC, but not ARM.
### Implementing the virtual hypercube ### Implementing the virtual hypercube