diff --git a/Implementing-post-scarcity-hardware.md b/Implementing-post-scarcity-hardware.md
index ab23a79..349d4b0 100644
--- a/Implementing-post-scarcity-hardware.md
+++ b/Implementing-post-scarcity-hardware.md
@@ -28,7 +28,8 @@ OK, OK, this cobe is a pretty concept, but let's get real. Using one core of eac
 There are other interesting chips which aren't strictly 64 core:
 
 1. [Cavium ThunderX](https://www.servethehome.com/exclusive-first-cavium-thunderx-dual-48-core-96-core-total-arm-benchmarks)/ - ARM; 96 cores, each 64 bit, in pairs of two, shipping now;
-2. [Sparc M8](https://www.servethehome.com/oracle-sparc-m8-released-32-cores-256-threads-5-0ghz/) - 32 of 64 bit cores each capable of 8 concurrent threads; shipping now.
+2. [Sparc M8](https://www.servethehome.com/oracle-sparc-m8-released-32-cores-256-threads-5-0ghz/) - 32 of 64 bit cores each capable of 8 concurrent threads; shipping now;
+3. [Parallela Epiphany](https://www.parallella.org/board/) is a family of processors designed for parallel computation, with a 64 core unit shipping now and a 1024 core unit in prototype. Development boards are cheap. The processor architecture is RISC, but not ARM. 
 
 ### Implementing the virtual hypercube